David Lammers, News Editor -- Semiconductor International, 7/28/2009
GlobalFoundries (Sunnyvale, Calif.) plans to apply embedded silicon
carbon (eSiC) stressors on its 22 nm nFET transistors, and is likely to
use through-silicon vias (TSVs) to connect a fast SOI-based DRAM layer
to a logic die, said John Pellerin, director of technology development
at the IBM/GlobalFoundries Alliance in Fishkill, N.Y.
In an interview prior to last week's groundbreaking ceremony
for the GlobalFoundries Fab 2 in Malta, N.Y., Pellerin said
GlobalFoundries and its Fishkill partners, including Applied Materials
Inc. (Santa Clara, Calif.), have largely solved the technical challenges
of eSiC stressors. By moving to an in situ phosphorous doping scheme
for the grown stressor layers, the researchers are able to stabilize
the carbon atoms and sharply improve carrier mobility and drive
current, he said.
At SEMICON West, Applied Materials touted its role in eSiC development with GlobalFoundries, including a new cleaning module for its deposition tool.
The move to TSVs is built upon IBM's work in developing an embedded
DRAM in an SOI substrate. Pellerin said the SOI eDRAM has a fast access
time but a relatively short retention time, requiring frequent refresh
cycles.
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