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IBM's POWER6 dual core pop's the cork at 4.7 Ghz!
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Written by Daniel   
Monday, 21 May 2007 15:50
IBM's POWER6 flies the coop at 4.7GHz
ARS Technica
By Jon Stokes | Published: May 21, 2007 - 02:11PM CT

Ah, if only Apple would've stuck with PowerPC, maybe it could've skipped the magical 3GHz mark and jumped straight to 4.7GHz. Okay, that's really just a cheap shot, but I couldn't resist, given today's major announcement by IBM that the 65nm POWER6 will not only debut next month at a stratospheric 4.7GHz, but it also shreds most of the relevant benchmarks. But before we get into the details, let's take a look at the basics of what was announced. From IBM's press kit, shorn of some of the marketspeak and with some of the details expanded:


Top frequency of 4.7GHz
>790 million transistors
341mm2 die size
65nm SOI process with ten layers of copper interconnect and a low-k dielectric on the first eight levels
Dual-core
Two-way simultaneous multithreading (SMT) on each core
Two memory controllers
Manufactured at IBM's 300mm semiconductor fab at East Fishkill, NY

With the exception of the actual top frequency number, all of the details above have been reported here previously. In fact, you might recall that at this past year's ISSCC, IBM claimed that POWER6 would debut north of the 5GHz mark, so Big Blue fell a bit short on that score. But such a shortcoming is pretty forgivable when you consider the fact that POWER6 has the same number of pipeline stages as its predecessor (15 integer stages), and it doesn't draw much more power.

My previous coverage of IBM's ISSCC revelations mentioned that serious questions remain about the POWER6 core architecture; questions on which IBM has kept decidedly mum. These questions center on the chip's out-of-order execution capabilities or the potential lack thereof. It's a good bet that one of the tricks that IBM used to get POWER6's clockspeed up so high was that the design team stripped away a ton of complexity from the pipeline by removing the out-of-order execution window. IBM has stated that floating-point instructions can issue out-of-order, but such issuing is certainly very limited in order to cut down on bookkeeping overhead.

Ultimately, there's a lot that can and should be said about what IBM did to bring about such a dramatic boost in clock frequency with POWER6, but that will have to wait for a separate article. In the meantime, let's take a look at the fruits of IBM's success.
Benchmark bombshell... More!

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