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IBM's 8-core POWER7: twice the muscle, half the transistors
Written by Daniel   
Wednesday, 02 September 2009 12:03

   IBM's 8-core POWER7 crams an amazing amount of hardware into about half the space of the competition. Its secret is that its large shared cache is made of DRAM, and not the less-dense SRAM that processors normally use.

By Jon Stokes | Last updated September 1, 2009 8:15 AM CT

IBM's Hot Chips presentation on its forthcoming 45nm POWER7 server processor had a wealth of information on the chip, which, at 1.2 billion transistors and 567mm2, is actually quite svelte considering what it offers. The secret is the first use of a special cache technology that IBM has been touting since 2007, but more on that in a moment.

POWER7 will come in 4-, 6-, and 8-core varieties, with the default presumably being the 8-core and the lower-core variants being offered to improve yields. Each core features 4-way simultaneous multithreading, which means that the 8-core will support a total of 32 simultaneous threads per socket. POWER7 is designed for multisocket systems that scale up to 32 sockets, which means that a full 32-socket system of 8-core parts would support 1024 threads.

Feeding eight cores in a single socket is quite a challenge, which is why each POWER7 has a pair of four-channel DDR3 controllers that can support up to 100GB/s of sustained memory bandwidth. Also helping the situation is a whopping 32MB of on-die L3 cache—IBM was able to cram this much cache on there by using a special embedded DRAM (eDRAM) design that cuts the transistor cost of its large cache pool roughly in half.  [ARS Technica...]     [Comments...]
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