Recently, we ran a story about Intel's research into carbon nanotube technology, and its application to semiconductor manufacturing. The take-home message from that story was that carbon nanotube tech looked promising, but was still quite a few years away from practicality, mainly due to issues with being able to repeatably produce reliable semiconducting nanotubes and integrate them into a standard silicon-based semiconductor manufacturing process..

Then I came across Nantero's web site.

Nantero is a company that was founded in 2001 by Greg Schmergel, Dr. Thomas Rueckes, and Dr. Brent M. Segal. The company's objective was to take technology invented by Dr. Rueckes and turn it into a commercially viable product. To date, Nantero have received over US $31 million in funding, and have partnerships with ON Semiconductor, LSI Logic, ASML, Brewer Science, and BAE Systems.

Ok, so they have some wizard looking tech, and they've managed to get some funding. What have they done? For starters, in 2003 they manufactured a 10 Gb array of carbon nanotube switches on a wafer using standard semiconductor manufacturing processes. In 2005, they manufactured and successfully tested a carbon nanotube switch just 22 nm in size. Finally, November 1 they announced that they had "resolved all of the major obstacles that had been preventing carbon nanotubes from being used in mass production in semiconductor fabs".

So, what exactly are they developing, and why should overclockers like us care? Put simply, Nantero have been working on, among other things, a new kind of RAM, dubbed NRAM™. This is to be a 'universal memory' that has the speed of 6-transistor static RAM, the density of single-capacitor dynamic RAM, and the persistence of FLASH. That's right, high-speed (REALLY high-speed), cheap, non-volatile memory.

Naturally when I read about this I became quite excited. After a brief discussion with Nantero's PR department, no less than Greg Schmergel (Nantero Co-founder and CEO) graciously agreed to an e-mail interview.

AOA: Thank you very much for granting me the opportunity to conduct an e-mail interview with you.  Would you like to make any opening comments before we get to the questions?

Greg Schmergel: No, your questions look very thorough so I'll just jump right in!

AOA: As I understand it, carbon nanotube manufacturing technology with respect to silicon processes is a rather 'hit and miss' proposition, resulting in highly variable product.  Can you discuss the difficulties with manufacturing carbon nanotubes generally, and then specifically related to silicon CMOS manufacturing processes?  Have you managed to overcome these problems?  If so, can you discuss how?

Greg Schmergel: There are several major obstacles which have prevented carbon nanotubes from being used in silicon CMOS fabs.  One is that carbon nanotubes come mixed with substantial metallic contamination, such as iron.  This makes it incompatible with a CMOS fab right from the start.  A second is that no one had ever developed a method for reliably positioning carbon nanotubes on a silicon wafer in a mass production process.  We have overcome both of these problems, and many other problems, and are using carbon nanotubes in production CMOS fabs today.  We have developed methods for purifying carbon nanotubes to less than 25 parts per billion of any metallic contamination, which means they are now compatible with most fabs' standards.  Then we developed a method for positioning the nanotubes using only existing fab equipment.  The way we do it is to spin coat the nanotubes on the wafer and then pattern the resulting nanotube fabric using lithography and etching, which means what is left at the end is only the nanotubes in the proper positions.  So this is now a very predictable process for using carbon nanotubes in mass production, and it can be done today.

AOA: Have you considered using the so-called 'bucky balls' instead of nanotubes?  If so, what prevented your use of them?  If not, why not?

Greg Schmergel: Buckyballs would not work for our application--if you look at the video of how our memory works on our Web page, you will see a tube is required.

AOA: Your web site indicates that you are developing a non-volatile RAM chip based on this technology.  Can you discuss this in more detail?  For example, will it be an exclusively carbon nanotube design, or will it mix silicon and carbon technology?  Will it use nanowires, semiconducting nanotubes, or some combination of the two?  Do you have a target speed? Can you discuss when this technology would become commercially available, and what the initial target markets might be?  Will it suffer from the same write-cycle lifetime limitations as current Flash-based storage?

Greg Schmergel: Our goal is a memory with the nonvolatility of flash, the speed of SRAM and the density of DRAM, all in one chip.  So to answer your question, the target speed is the same as SRAM and the target lifetime is also the same as SRAM--in other words, without the write cycle limitations of flash.    Our memory is a hybrid of carbon nanotubes and silicon--in fact, there is a lot more silicon in it than nanotubes!  But the nanotubes play a critical role.  We do not use nanowires.  The target markets include every electronic device, as we've found that a fast nonvolatile memory can add tremendous value to just about all of them!

AOA: One of the primary limiting factors of DRAM technology is the charge storage capacitor.  Its need for constant refreshing of the charge has resulted in many novel designs to 'hide' the recharging.  In addition, the need for sense amplifiers results in high single-cycle latencies; even the fastest commercial DRAMs are still in the 40-45 nS range for that first cycle, which represents a huge penalty to today's high-speed processors, and again there are many novel designs to try to 'hide' this latency.  Will memory designs based on carbon nanotubes be able to have an impact on this?

Greg Schmergel: Yes, NRAM (nanotube RAM) does not require refreshing--van der Waals forces hold the bits in their on state without any need for external power.

AOA: Power consumption is becoming a big issue in semiconductor design; some of the designs out there are now pushing thermal densities approaching the level of nuclear reactors.  Will carbon nanotubes have any effect on power consumption?

Greg Schmergel: Yes, we expect to help reduce power consumption in many ways, not least of which is that a fast nonvolatile memory would not require refreshing, so when you're not using the memory, it does not consume any power.  Plus it inherently takes very little power to write an NRAM bit.

AOA: It is safe to assume that you wouldn't be pursuing this technology if you didn't think it would be cost competitive with more conventional technologies.  When do you foresee this occurring?

Greg Schmergel: The process to manufacture NRAM requires very few steps and only one additional mask layer, so it is expected to be very cost competitive with conventional technologies in the future. 

AOA: Do you envision your carbon nanotube technology being implemented in CPUs and GPUs?  If so, what part of the chip do you see it impacting first?

Greg Schmergel: We do envision NRAM being used in CPUs and GPUs, as a replacement for the embedded cache (which is now SRAM) and as an embedded nonvolatile memory option, which gives the designers substantially more flexibility in being able to use nonvolatile memory on-chip without huge cost and complexity penalties.

AOA: Do you believe we will one day see entire ICs implemented using carbon nanotube technology?

Greg Schmergel: Eventually it will be possible to have the entire IC, including the transistors, the memory, and the interconnects, be made using carbon nanotubes.  In each area carbon nanotubes can bring big leaps forward in performance.

AOA: There was an article on CNET recently where it was mentioned that Intel are exploring carbon nanotube technology.  Have they approached you, and is this something you can discuss?  Have any other manufacturers approached you, and can you discuss those conversations?

Greg Schmergel: All our conversations with customers and potential customers are confidential, as you would expect.

AOA: Silicon processes are currently at 45nm feature size, with 30 on the horizon, and 22 coming.  However, there are looming limits of physics constraining our ability to manufacturer ever smaller silicon devices. 
Do you believe that carbon nanotube technology will allow us to scale to even smaller feature sizes than will ultimately be possible with silicon?

Greg Schmergel: Absolutely.  This is one of the major advantages of NRAM and of carbon nanotube technology in general.  Taking NRAM as an example, we have already made a 22nm working NRAM bit, and we believe NRAM will scale to below 5nm--certainly the physics works equally well at such small scales, as opposed to most silicon memories where limits occur well before that.  And as you scale NRAM down, nature works for us, and the memory works faster, with less power required. 

AOA: Do you have any final thoughts?

Greg Schmergel: No, your questions were very comprehensive!  I hope I managed to answer them to your satisfaction, and I do encourage you to visit our Web site and to see the video on the home page to see how the memory works, which will help you visualize how scalable it truly is as well.

AOA: Once again, thank you for granting me some of your time. 

There you have it folks.  Given that Nantero have proven the technology works in commerical fabs, I would be very surprised if we don't start seeing products utilizing this technology in the next 18-24 months, possibly sooner.  In fact, given the partnership with BAE, they may already be employing this tech in the military sector for radiation-hardened applications.

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