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NEC tips 40-nm process with high-k, eDRAM
Written by Gizmo   
Wednesday, 21 November 2007 00:05

Mark LaPedus
EE Times

SAN JOSE, Calif. — Seeking to stay ahead of the curve in ASICs, game-machine devices and other products, NEC Electronics Corp. has rolled out a 40-nm logic process that includes a pair of embedded DRAM technologies.


The 40-nm process makes use of a one-two punch: hafnium-based high-k dielectric materials and nickel-silicide gate electrodes. This process, to be shipped in the 2009 time frame, also uses zirconium-oxide DRAM capacitors

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The company also included high-k dielectric materials for gate-stack applications within its recently-introduced, 55-nm process, dubbed UX7LSeD. Intel, IBM and others have also announced high-k materials as well.


NEC Electronics and Toshiba Corp. are co-developing a 45-nm process, as part of a previously-announced partnership. NEC is said to be tweaking the process and will roll out its own version, which will be a 40-nm offering.


Like the 55-nm process, NEC Electronics has also incorporated an embedded DRAM or eDRAM technology into the mix. In fact, the company has a pair of eDRAM offerings: UX8GD and UX8LD.

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